The present invention relates generally to testing memory elements in integrated circuit devices for defects and using electronically programmed fuses to replace defective memory elements. More specifically, embodiments of the present invention are directed to interleaving memory repair data compression and fuse programming operations as a single combinable operation in a single fusebay architecture.
Embedded memories are generally the most dense components used in integrated circuit devices such as application specific integrated circuit (ASIC) and systems on chip (SOC) designs. During the manufacturing process of ASIC and SOC devices, these memories are sensitive to process defects that can cause failures. These memory failures may adversely impact the ability of ASIC and SOC devices to operate in their intended manner. In order to account for such failures, embedded memories are typically designed to have redundant memory in the form of additional columns, rows or locations. The redundant memory can be dynamically substituted for locations within a particular memory that have been diagnosed during a testing phase as exhibiting failure characteristics. Thus, when an ASIC or SOC device is powered up, information is conveyed to the memory, at the time of start up, instructing it to access a location within the redundant memory whenever a failed memory location is sought to be accessed. As long as the redundant memory locations may be accessed as proxies for failed memory locations, these memories are considered to be repaired and available for use within ASIC and SOC devices.
Electronically programmed fuses are typically used to repair the embedded memories with repair data that enables redundant memory locations to be accessed as proxies for failed memory locations. The fuses are typically polysilicon links that are electronically programmed to one of two logic states to represent repair data generated from built-in self tests (BISTs) of the memories that are performed during the testing phase. Typically, a “blown” fuse represents a logical “1”, while an intact fuse represents a logical “0”.
One type of self-test and repair architecture that has been used with integrated circuit devices such as ASIC and SOC devices includes the use of multiple fusebays to program repair data. In such an architecture, a primary fusebay, a secondary fusebay and a tertiary fusebay are used in conjunction with a fuse controller to fuse repair data based on performing three repair passes of the memories. The primary repair pass, which is done at wafer level, performs the majority of the fuses, while the secondary repair pass performs less fuses and the tertiary repair performing even fewer fuses. In particular, during the primary repair pass, repair data that is stored in a repair register is unloaded from the register upon completion of the BISTs and compressed by the fuse controller. This compressed data is then stored in the primary fusebay. In the secondary repair pass, the BISTs are rerun with the primary repair solutions generated from the prior tests. New failures are added to the repair register and are unloaded and compressed by the fuse controller upon completion of the BISTs. This compressed data is then stored in the secondary fusebay. Similarly, during the tertiary repair pass, BISTs are rerun with the primary and secondary repair solutions, and any new failures are compressed and stored in the tertiary fusebay. The final repair solutions for the memories are then obtained by first decompressing the repair solutions from each of the fusebays and then performing fusing and comparison operations.
A benefit of using a multi-fusebay architecture that includes a primary fusebay, a secondary fusebay, and a tertiary fusebay is that the compressing of repair data followed by programming of the repair data occurs simply as two separate operations. More specifically, all of the repair data is compressed in one operation and then all of the compressed repair data is programmed in another separate operation. However, with the ever increasing number of fuses being used in integrated circuit devices (sometimes doubling with each successive technology node), the amount of logic associated with each individual fuse is prohibitively excessive with respect to maintaining competitiveness in area overhead.